1. Technical Field
This invention relates generally to resistive memory arrays, and more particularly, to fabrication and use of P-I-N diodes as part of the array.
2. Background Art
FIG. 1 illustrates a resistive memory array 60. The array 60 includes a first plurality of parallel conductors 62 (bit lines) BL0, BL1, . . . BLn, and a second plurality of parallel conductors 64 (word lines) WL0, WL1, . . . WLn overlying and spaced from, orthogonal to, and crossing the first plurality of conductors 62. A plurality of memory structures 66 are included in the array. Each memory structure 66 includes a resistive memory cell 68 and a diode 70 in series therewith connecting a conductor WL of the plurality thereof with a conductor BL of the plurality thereof at the intersection of those conductors, with the diode 70 in a forward direction from the conductor WL to the conductor BL. For example, as shown in FIG. 1, in the memory structure 6600, resistive memory cell 6800 and diode 7000 connect in series WL0 with BL0; in the memory structure 6601, resistive memory cell 6801 and diode 7001 connect in series connect WL1 with BL0, etc.
The diodes 70 have the conventional PN configuration shown in FIGS. 2 and 3, including a P+ region in contact with an N+ region. As is well known, a diode of this type, having a relatively low forward threshold voltage, readily conducts current in the forward direction upon application of forward potential thereto (FIG. 2), but having a relatively high reverse breakdown voltage, does not conduct substantial current upon application of reverse potential thereto (FIG. 3).
Because of this characteristic, these diodes 70 (oriented as shown in FIGS. 1, 4 and 5) are used as select devices in the array 60 of FIG. 1. FIGS. 1, 4 and 5 illustrate this utility.
FIG. 1 illustrates the programming of a selected resistive memory cell 6800 of the array 60. In such programming, Vpg is applied to word line WL0, and 0V is applied to bit line BL0 and word lines WL1 . . . WLn. Meanwhile, Vpg is applied to bit lines BL1 . . . BLn. This causes a voltage Vpg to be applied across the memory structure 6600, in the forward direction from the word line WL0 to the bit line BL0, sufficient to program the resistive memory cell 6800. All other resistive memory cells connected to the word line WL0 and bit line BL0 have 0V potential thereacross. Meanwhile, all the other resistive memory cells of the array 60 have Vpg applied thereacross in the reverse direction of the diode 70, with Vpg applied thereto being less than the reverse breakdown voltage of the diode 70. In this way, the diodes throughout the array 60 act as select devices to ensure that only the selected resistive memory cell is programmed and that the other resistive memory cells of the array are undisturbed.
FIG. 4 illustrates the erasing of the selected resistive memory cell 6800 of the array 60. In such erasing, Ver (lower voltage than Vpg) is applied to word line WL0, and 0V is applied to bit line BL0 and word lines WL1 . . . WLn. Meanwhile, Ver is applied to bit lines BL1 . . . BLn. This causes a voltage Ver to be applied across the memory structure 6600, in the forward direction from the word line WL0 to the bit line BL0, which (along with increased current applied through the resistive memory cell 6800 as compared to programming current) is sufficient to erase the resistive memory cell 6800. All other resistive memory cells connected to the word line WL0 and bit line BL0 have 0V potential thereacross. Meanwhile, all the other resistive memory cells of the array 60 have Ver applied thereacross in the reverse direction of the diode 70, with Ver applied thereto being less than the reverse breakdown voltage of the diode. In this way, the diodes throughout the array 60 act as select devices to ensure that only the selected resistive memory cell is erased and that the other resistive memory cells of the array are undisturbed.
FIG. 5 illustrates the reading of the selected resistive memory cell 6800 of the array 60. In such reading, Vr (lower voltage than Ver) is applied to word line WL0, and 0V is applied to bit line BL0 and word lines WL1 . . . WLn. Meanwhile, Vr is applied to bit lines BL1 . . . BLn. This causes a voltage Vr to be applied across the memory structure 6600, in the forward direction from the word line WL0 to the bit line BL0, sufficient to read the state of the resistive memory cell 6800. All other resistive memory cells connected to the word line WL0 and bit line BL0 have 0V potential thereacross. Meanwhile, all the other resistive memory cells of the array 60 have Vr applied thereacross in the reverse direction of the diode 70, with Vr applied thereto being less than the reverse breakdown voltage of the diode. In this way, the diodes throughout the array 60 act as select devices to ensure that only the selected resistive memory cell is read and that the other resistive memory cells of the array are undisturbed.
While such an approach is useful, it will be understood that diodes of this type may exhibit an undesirable degree of current leakage, potentially resulting in undesired disturbing of other cells, along with a high level of power consumption. Meanwhile, it will be understood diodes used as select devices should provide high driving capability. What is needed is an approach wherein select devices in a resistive memory array exhibit very low current leakage along with high driving capability. What is further needed are methods for fabricating structures which are capable of providing these features, which methods are simple and efficient.